A floating point multiplier performing IEEE rounding and addition in parallel

This work was one of ASIC basis technology project mainly managed by IDEC and supported by the ministry of trade, industry & energy and the ministry of science and technology of korea. Abstract In the conventional oating point multipliers, the rounding stage is usually constructed by using a high speed adder for the increment operation, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it may accompany additional execution time and hardware components for renormalization which may occur by an overrow from the rounding operation. A oating-point multiplier performing addition and IEEE rounding in parallel is designed by optimizing the operational ow based on the characteristics of oating point multiplication operation. A hardware model for the oat-ing point multiplier is proposed and its operational model is algebraically analyzed in this research. The oating point multiplier proposed does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-eeective design can be achieved by this approach.